1. Field of the Invention
The present invention relates to a semiconductor memory device having twin wells and a manufacturing method thereof.
2. Description of Related Art
There are a variety of different types of SRAMs, one form of semiconductor memory devices. One type of SRAMs employs CMOS devices. Among CMOS devices, twin-well type devices are mainstream devices. A twin-well type device has a p-well and an n-well that are formed in a semiconductor substrate. For example, Japanese Unexamined Patent Publication No. 8-330528 describes an SRAM employing twin wells. FIG. 18 is a cross-sectional view showing a memory cell-area and a peripheral circuit area of the SRAM described in the publication.
The construction of the memory cell area is discussed first. A semi-recessed LOCOS oxidation layer 204 is formed on the main surface of a silicon substrate 200. A p-well 202 is formed over the entire surface of the main surface of the silicon substrate 200. The p-well 202 extends to a level deeper than the semi-recessed LOCOS oxidation layer 204.
An n-well 206 is formed in a predetermined area of the p-well 202. The n-well 206 is formed at a level shallower than the semi-recessed LOCOS oxidation layer 204. A p-channel transistor 208 having a pair of p-type source/drains 210 is formed in the n-well 206.
An n-channel transistor 214 having a pair of n-type source/drains 212 is formed in a predetermined area of the p-well 202. The n-channel transistor 214 is isolated from the p-channel transistor 208 by the semi-recessed LOCOS oxidation layer 204.
The construction of the peripheral circuit area is now discussed. A semi-recessed LOCOS oxidation layer 216 is formed on the main surface of the silicon substrate 200. A p-well 218 and an n-well 220 are formed on the main surface of the silicon substrate 200. The border between the p-well 218 and the n-well 220 is present beneath the semi-recessed LOCOS oxidation layer 216. The depths of the p-well 218 and the n-well 220 are generally equal to the depth of the p-well 202.
A p-channel transistor 224 having a pair of p-type source/drains 222 is formed in the n-well 220. A n-channel transistor 228 having a pair of n-type source/drains 226 is formed in the p-well 218.
To miniaturize memory cells, the length of the device isolation structure (such as a semi-recessed LOCOS oxidation layer) of the memory cell area needs to be shortened. To prevent the generation of a substrate current that causes latchup, the spacing between one well and the source/drain of another well formed adjacent to the one well needs to be longer than a certain distance.
In the technique discussed in the above publication, the n-well 206 is formed at a level shallower than the semi-recessed LOCOS oxidation layer 204. This arrangement prevents the distance between the n-well 206 and the n-type source/drain 212 from becoming too short while providing the semi-recessed LOCOS oxidation layer 204 with an adequate length.
In the technique disclosed in the publication described above, however, the depth of the p-well 202 is different from the depth of the n-well 206. This arrangement creates a difference in performance between the n-channel transistor 214 and the p-channel transistor 208. This leads to an imbalance between the n-channel transistor 214 and the p-channel transistor 208, degrading a state-sustaining function of each flip-flop in the SRAM.
Furthermore, the p-type source/drain 210 is formed in the n-well 206, and the n-well 206 is formed at a level shallower than the semi-recessed LOCOS oxidation layer 204. Accordingly, this arrangement leads to a problem as to how a well contact region that connects to a wiring for fixing the potential of the n-well 206 is formed. Forming the well contract region in each cell is contemplated. However, such a construction increases the cell size.
A shallow n-well 206 requires that the p-type source/drain 210 be formed at a considerably shallower level. The drain current of the p-channel transistor 208 is substantially smaller than the drain current of the n-channel transistor 214. When an operating voltage is high, this is not a problem. However, the operating voltage is lowered as the SRAM is miniaturized. For example, when the p-channel transistor 208 is operated from 2 V, there is fear that a small current causes the p-channel transistor 208 to be unable to achieve its required performance.
The present invention has been developed to solve the above-described problems. It is an object of the present invention to provide a semiconductor memory device and a manufacturing method thereof, which prevents the distance between one well and the source/drain of another well form-ed adjacent to the one well from becoming too short without increasing the length of the device isolation structure.
In accordance with one embodiment of the present invention, a semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device may include a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. In one feature of the embodiment, the second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is generally equal in depth to the second well, wherein the second and third wells are formed down to a level lower than the device isolation structure.
In accordance with one embodiment of the present invention, the well in the peripheral circuit area and the wells in the memory cell area may be different in depth. In a preferred embodiment, the depths of the second and third wells formed in the memory cell area are shallower than that of the first well formed in the peripheral circuit area.
In accordance with one embodiment of the present invention, the second well and the third well beneath the device isolation structure may overlap with one another, and an overlapped area between the second well and the third well beneath the device isolation structure is reduced. The reason for this will be described in the discussion of the embodiments.
In one feature of an embodiment of the present invention, the distance between one well and the source/drain of another well formed adjacent to the one well is prevented from becoming too short without increasing the length of the device isolation structure.
Examples of the device isolation structure in the present invention include a LOCOS oxidation layer, a semi-recessed LOCOS oxidation layer, a shallow trench (as deep as 0.4 to 0.8 xcexcm), and the like. The term xe2x80x9csource/drainxe2x80x9d refers to at least one of source and drain.
In accordance with one embodiment of the present invention, the second well and the third well may be equal in depth. This arrangement precludes an imbalance in performance between transistors attributable to a well depth difference in the memory cell area. It is noted that, in this specification, the term xe2x80x9cequal depthxe2x80x9d is not strictly limited to the same depth but also covers a well depth difference that causes substantially no imbalance in performance between transistors.
Since the second well and the third well may be equal in depth in accordance with embodiments of the present invention, the depth of the source/drain of the second well and the depth of the source/drain of the third well can be equalized to one another. This arrangement causes substantially no imbalance in performance between transistors, attributable to a depth difference between the sources/drains in the memory cell area.
In accordance with one embodiment of the present invention, the sources/drains formed in the second well and third well are prevented from becoming too shallow, compared to the source/drain formed in the first well.
The well contact region for fixing the well potential is formed isolated from the source/drain. In accordance with one embodiment of the present invention, the second and third wells are formed down to a level lower than the device isolation structure. With this arrangement, the wells can extend to the well contact region. The second and third wells are thus readily connected to the well contact regions.
In accordance with one embodiment of the present invention, the depths of the source/drain of a transistor formed in the first well, the depths of the source/drain of a transistor formed in the second well, and the depths of the source/drain of a transistor formed in the third well may preferably be equal to one another. With this arrangement, the sources/drains having the same conductivity type can be produced at the same time.
The first, second and third wells may preferably be retrograded wells in accordance with one embodiment of the present invention. The retrograded well refers to a well that is produced using a high-energy ion implantation, rather than thermal diffusion.
Each of the retrograded wells, i.e., the first, second and third wells, includes, in the order from above, a first-concentration layer, a second-concentration layer and a third-concentration layer. The first well may further include a fourth-concentration layer beneath the third-concentration layer. In one embodiment, in the first well, a channel doped layer for adjusting Vth of a transistor, for example, is the first-concentration layer; a punch-through stopper layer for controlling a short channel effect of the transistor, for example, is the second-concentration layer; a channel cut layer for restraining the operation of a parasitic transistor in the device isolation structure, for example, is the third-concentration layer; and a low-resistance layer for lowering the well resistance, for example, is the fourth-concentration layer. In the second and third wells, a channel doped layer, for example, is the first-concentration layer, a punch-through stopper layer, for example, is the second-concentration layer and a channel cut layer, for example, is the third-concentration layer.
In accordance with one embodiment of the present invention, a CMOS cell type SRAM is formed in the memory cell area. The CMOS cell type SRAM refers to an SRAM in which each cell is constructed of CMOS.
In accordance with embodiments of the present invention, the length of the device isolation structure in the memory cell area preferably falls within a range of about 0.2 xcexcm to 1.6 xcexcm. The border between the second well and the third well needs to be located beneath the device isolation structure. There is a possibility that a misalignment takes place when a resist is patterned. For this reason, the device isolation structure thus needs a minimum length. The minimum length of the structure is about 0.2 xcexcm. If the length of the device isolation structure is longer than about 1.6 xcexcm, the size of a memory cell becomes too large.
The depth of each of the second and third wells preferably falls within a range of about 0.5 xcexcm to 1.2 xcexcm in accordance with embodiments of the present invention. If the depths of the second and third wells are shallower than about 0.5 xcexcm, the device isolation structure becomes deeper than the wells. There arises a problem as to how a well contact region for fixing the potential of the well is formed. If the depths of the second and third wells are deeper than about 1.2 xcexcm, the overlapped area between the second well and the third well, beneath the device isolation structure, expands.
The first well may preferably include a first conductivity type well and a second conductivity type well, in other words, may preferably include twin wells.
When the first, second and third wells in the structure have their impurity concentrations varying in the direction of depth of the structure, the first well of the first conductivity type and the second well can be concurrently produced, and the first well of the second conductivity type and the third well can be concurrently produced. For example, in one embodiment, the first well may have four layers having four different impurity concentrations, and each of the second and third wells may have three layers of three different impurity concentrations. The fourth-concentration layer may be formed in each of the first wells of the first and second conductivity types. Each of the third-concentration layer, the second-concentration layer, and the first-concentration layer may be formed on the first well of the first conductivity type and the second well at the same time, and each of the third-concentration layer, the second-concentration layer, and the first-concentration layer may be formed on the first well of the second conductivity type and the third well at the same time.
In accordance with one embodiment of the present invention, a semiconductor memory device having a semiconductor substrate, a peripheral circuit area and a memory cell area on a main surface of the semiconductor substrate is manufactured by the following manufacturing method: (a) a device isolation structure is formed on the main surface of the semiconductor substrate; (b) a first well is formed by ion-implanting an impurity in the peripheral circuit area only; (c) a second well of a first conductivity type is formed by ion-implanting an impurity in the memory cell area, wherein the second well is shallower in depth than the first well and is formed down to a level lower than a device isolation structure; and (d) a third well of a second conductivity type is formed by ion-implanting an impurity in the memory cell area, wherein the third well is in contact with the second well beneath the device isolation structure and is generally equal in depth to the second well.
As a result, a semiconductor memory device prevents the distance between one well and the source/drain of another well adjacent to the one well from becoming too short without excessively elongating the device isolation structure.
In a preferred embodiment, step (b) may preferably use, as a mask, a resist pattern having a thickness within a range from about 3.0 xcexcm to about 8.0 xcexcm, and steps (c) and (d) may preferably use, as a mask, a resist pattern having a thickness within a range from about 1.2 xcexcm to about 2.5 xcexcm.
If the thickness of the resist pattern is thinner than about 3.0 xcexcm in step (b), an impurity penetrates the resist pattern when ion implantation is performed to form a retrograded well. If the thickness of the resist pattern is thicker than about 8.0 xcexcm, control of the configuration of the end portion of the resist pattern is difficult. As a result, the length of the device isolation structure needs to be increased.
If the thickness of the resist pattern is thinner than about 1.2 xcexcm in steps (c) and (d), an impurity penetrates the resist pattern when ion implantation is performed to form a retrograded well. If the thickness of the resist pattern is thicker than about 2.5 xcexcm, there arises a problem that the overlapped area between the second well and the third well, beneath the device isolation structure, expands.
Either a positive resist or a negative resist works as the resist pattern in step (b). A positive resist or a negative resist works as the resist pattern in steps (c) and (d) as well. However, more preferably, a positive resist is used in steps (c) and (d). This is because the positive resist outperforms the negative resist in the control of the vertical configuration of the end portion of the resist pattern and the dimensional control of the resist pattern.
The first well, constructed in accordance with the manufacturing method of the present invention, may preferably be composed of a first conductivity type well and a second conductivity type well, in other words, twin wells. Step (b) may include implanting ions in a formation area of the first conductivity type well and implanting ions in a formation area of the second conductivity type well.
Step (c) may include the step of implanting ions three times in the formation area of the second well and the formation area of the first conductivity type well in the peripheral circuit area. By the step of implanting ions three times, the second well has, in the order from below, a third-concentration layer, a second-concentration layer and a first-concentration layer formed in the memory cell area. By step (b) and the step of implanting ions three times, the first conductivity type well has, in the order from below, a fourth-concentration layer, a third-concentration layer, a second-concentration layer and a first-concentration layer formed in the peripheral circuit area.
Step (d) may include the step of implanting ions three times in the formation area of the third well and the formation area of the second conductivity type well in the peripheral circuit area. In the step of implanting ions three times, the third well has, in the order from below, a third-concentration layer, a second-concentration layer, and a first-concentration layer, is formed in the memory cell area. In step (b) and the step of implanting ions three times, the second conductivity type well has, in the order from below, a fourth-concentration layer, a third-concentration layer, a second-concentration layer, and a first-concentration layer, formed in the peripheral circuit area.